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Silicon Labs Programmable Product Request Form

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Applicable parts: Si5121x: Tiny Clock; Si5213x: Programmable PCIe clocks; Si54090/Si54091: 4PLL with OTP (consider using Si5350 instead); SL15300: 1PLL with EEPROM (consider using Tiny Clock instead); SL38000: 4PLL (consider using Si5350 instead); SL28PCIexx: Programmable PCIe clock (consider using Si5315x instead).

Category




Category




Date




SiLabs Sales Person




Target part for customization




Alternate part (if applicable)




Customer Company Name




Targeted application




Volume in K/year




Target price




Required sample date




Required sample quantities




Mass production date




Product lifecycle




Required temp range




Current solution and / or competitive part number





Please complete table1. If items are left unspecified, it is assumed customer does not need the item, or can accept any variable (e.g., xtal input frequency). Attach block diagram if available.

Input / Output

Target SOC Application

Target Center Freq (MHz)

Output type and Voltage

Spread %

CCJ

fTOL

(± ppm)

fACC

(± ppm)

VDD Typ. (V)

Other Key Parameters / Comments

CLK1

Example: Wi-Fi

Example: 40MHz

Example: LVCMOS



















CLK2




























CLK3




























REFCK1




























Xin / Xout

Crystal input






















Example: VCXO pull range (+/-ppm): _____

Example: Xtal CL; CL(pF): ____

Clock in

External clock

























1 – Column Field Definitions:

Input / Output type and Voltage: Required output type with specified swing level (e.g. 1.8V LVCMOS, 2.5V LVCMOS, 3.3V LVCMOS, HCSL/PCIe, etc.).

Spread: If spread spectrum EMI reduction is required, list all desired spread options (e.g. -0.5%, +/-0.25%, -1%, +/-0.5%).

CCJ: The cycle to cycle jitter requirements for 10,000 clock periods CCJ = Absval(+/-CCJ). (list Max and NOTE THE UNITS (s / ns / ps).

FTOL: Frequency tolerance at 25C requirement excluding crystal error (total allowable output error (ppm) - crystal spec (ppm)) (e.g. (+/-50) – (+/-30) = +/-20).

FACC: Frequency accuracy across temp requirement excluding crystal error (total allowable output error (ppm) - crystal spec (ppm)) (e.g. (+/-50) – (+/-30) = +/-20).

VDD Typ: Typical power supply spec for this output. Generally this is the same for all outputs unless some are running on separate VDD planes.

Other Key Parameters/Comments: List any of the following if applicable:

  1. LTJ/Dly/Acq

    1. LTJ: Long Term Jitter requirements (e.g., 800pS) [LTJ = max – min, of accumulated jitter].

    2. Dly: Time delay setting for measurement (e.g., 10s).

    3. Acq: Number of acquisitions to be measured (e.g., 1000).

  2. Duty Cycle: The duty cycle limits (e.g. 45%-55%).

  3. Tr/Tf: Rise and fall times measured at 20%-80% of VDD, specify whether min, max or typ.

  4. CL: For output clocks this is the total load capacitance driven by the output and includes estimated trace capacitance and the receiver input capacitance. If the I/O signal is Xin/Xout, then CL refers to the load capacitance of the crystal taken from the crystal datasheet.

  5. VCXO: If applicable, enter desired pull range and crystal parameter C0/C1 (to determine if crystal is pull-able).




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